Field of the Invention
The invention relates to chip package technology, and in particular to a chip package and methods for forming the same.
Description of the Related Art
The chip packaging process is an important step in the fabrication of an electronic product. Chip packages not only protect the chips therein from outer environmental contaminants, but they also provide electrical connection paths between the electronic elements inside and those outside of the chip packages.
In general, chip packages with a sensing function comprise a conducting layer formed on the upper surface of chips. The conducting layer forms external electrical connection paths of a signal contact pad. Subsequently, the conducting layer is electrically connected to a circuit board through wires.
However, in the aforementioned method, multiple layers (e.g., insulation layers) are usually deposited on sensing regions of chips. As a result, sensitivity of the sensing regions is reduced. Furthermore, the entire height of the chip packages is also limited to the height of wires. As a result, it is difficult to further decrease the size of electronic products with a sensing function.
Thus, there exists a need in the art for development of a chip package and methods for forming the same capable of mitigating or eliminating the aforementioned problems.